1. Technical Field
The disclosure relates to a switchable integrated electronic device, to electronic circuits incorporating the switchable integrated electronic device, and to a method of manufacturing a switchable integrated electronic device, and in particular the layout of such devices and circuits.
2. Description of the Related Art
The growth of the semiconductor industry is driven by the rapid development and evolution of applications such as wireless communications, imaging processing, internet, and entertainment. In order to reach a high-level of circuit integration and reduce the cost and size, and to enhance competitiveness, analog and mixed-signal circuits are implemented in standard CMOS. Recently, RF and power management functions are increasingly integrated on a digital chip. Device matching is very critical for these circuits, and it is well recognized that the yield and cost can be strongly affected by the design technique adopted, particularly the layout of matching-critical devices. These devices can be transistors, capacitors, inductors or resistors. Matching has become critically important since the process technology is driven by digital circuits where matching is not important.
The matching properties of transistors have been considered by K. Lakshmikumar et al in ‘Characterization and modeling of mismatch in MOS transistors for precision analog design’, IEEE J. Solid-State Circuits, vol. 21, pp. 1057-1066, December 1986 and by M. Pelgromet al in ‘Matching properties of MOS transistors’, IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, October 1989, and of transistors and capacitors by J. Shyu et al in ‘Random error effects in matched MOS capacitors and current sources’, IEEE J. Solid-State Circuits, vol. 19, pp. 948-956, December 1984. The matching properties of resistors have been considered by Y. Lin et al in ‘Resistor layout techniques for enhancing yield in ratio-critical monolithic application’, Proc. NWSCAS 2001, vol. 1, pp. 259-261, 2001. Proposed layout techniques, such as common-centroid, deal with matching of two closely placed MOS transistors of equal size only. In practical circuit design, what is frequently required are two devices having large and varying non-unity ratios, which must be precisely matched, which may be referred to as ratio matching. Unfortunately, the layout techniques developed for equal size devices cannot be directly applied to ratio matching.
Resistor layout differs somewhat from that of transistor layout. Straight-line resistors are usually avoided and each resistor is implemented by a series/parallel combination of a number of unit resistors. The most popular layout technique is interleaving. FIG. 1 shows an example of an amplifier where resistors R1 (non-shaded) and R2 (shaded) are implemented each using 9 resistor elements, with R1=R2. The node between R1 and R2 is denoted X. This configuration provides a fixed gain. In many systems a programmable gain amplifier is required and very often the gain must vary over a large range in a certain step size. If the gain is non-unity but fixed, it may still be possible to interleave the resistor elements of R1 and R2 to achieve good matching between R1 and R2. However, device matching becomes more problematic when the resistance ratio is not only large but also varying. For example, automatic gain control for cellular phones generally requires a gain range from −40 dB to +8 dB, in 4 dB steps. In this case, the resistance ratio R2/R1 has to vary from 0.01 to 2.51. As the gain varies, either R1 or R2, or both, must vary. As a result the constellation of R1 and R2, by which we mean the interleaving arrangement of R1 and R2, also varies. If the layout for R1 and R2 is optimized at one gain setting, switching to another gain causes the layout of R1 and R2 to be no longer optimum. This problem is exacerbated if the gain variation and the number of gain steps is large. There exists a need to improve the matching of components with large and varying component ratios.